1. Technical Field
The present invention relates generally to a semiconductor device, and more particularly, to a semiconductor device including an error check and correction (hereinafter referred to as ‘ECC’) circuit.
2. Related Art
After fabricating semiconductor memory devices, a defective memory cell is selected by performing a test. For example, a semiconductor memory device may be equipped with a circuit having an ECC function in order to improve the yield of the device.
The ECC circuit performs a function of detecting and correcting defective data in real time and adds additional parity bits to DQ bits when the DQ data of memory is transmitted. A semiconductor memory device detects a data error in DQ bits by checking whether the added parity bits, together with the DQ bits, are transmitted or not according to a specific rule. The number of DQ bits that can be verified and corrected may be limited depending on the number of parity bits. In other words, the number of parity bits restricts data error detection since error checking is done on the combination of parity bits and DQ bits. For example, if 2 parity bits are added to a DQ of 16 bits, “2-bit detection and 1 bit correction” may be generated by an ECC algorithm. Thus, in the case of this ECC circuit, an operation correction capability using parity bits may be limited.